Programmable logic enabled dynamic offset cancellation

An integrated circuit comprising:

• a buffer circuit having an offset cancellation circuit configured to receive an offset control signal;
• and
• programmable logic coupled to the buffer circuit and configured to monitor one or more signal offsets of the integrated circuit and to generate the offset control signal in response thereto,
• wherein the offset control signal generated by the programmable logic can compensate for offset in the buffer circuit, and
• wherein the buffer circuit comprises:
• a differential amplifier having first and second differential input transistors;
• and
• a de-skewing circuit coupled to the first and second differential input transistors.

A programmable logic device comprising:

• a differential input buffer including:
• a pair of differential input transistors that receive and amplify a differential input signal, and
• a de-skewing circuit coupled to the differential input transistors and configured to receive an offset control signal;
• a signal processing block coupled to the differential input buffer and configured to generate a processed signal in response to the differential input signal;
• and
• programmable logic coupled to the signal processing block and configured to receive the processed signal and to generate the offset control signal in response to the processed signal, wherein the programmable logic is configured to monitor device performance and to cancel offsets in the differential input buffer when needed.