US 7,321,132 B2 · Multi-layer structure for use in the fabrication of integrated circuit devices and methods for fabrication of same

Abstract

A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

Claims14

Dependent claims

A multi-layer structure for use in the fabrication of integrated circuit devices, comprising:

a buffer layer on a substrate;
a channel layer on said buffer layer;
a spacer layer on said channel layer;
a first Schottky layer on said spacer layer;
a second Schottky layer overlying said first Schottky layer;
a third Schottky layer overlying said second Schottky layer;
a contact layer overlying said third Schottky layer;
said structure having defined therein:
a first etch-stop intermediate said first Schottky layer and said second Schottky layer;
a second etch-stop intermediate said second Schottky layer and said third Schottky layer;
and
a third etch-stop intermediate said contact layer and said third Schottky layer.

9 more elements

Dependencies are inferred from the claim text.

Multi-layer structure for use in the fabrication of integrated circuit devices and methods for fabrication of same

Life of this patent

Multi-layer structure for use in the fabrication of integrated circuit devices and methods for fabrication of same

Life of this patent

Abstract

Claims14