Counter circuit, AD conversion method, AD converter, semiconductor device for detecting distribution of physical quantities, and electronic apparatus

An analog-to-digital conversion method for convening a difference signal component into digital data, the difference signal component representing a difference between a reference component and a signal component included in an analog signal subject to processing, the method being carried out using an asynchronous counter circuit that is allowed to selectively perform counting in an up-count mode or counting in a down-count mode and comprising the steps of:

• in a first processing iteration, comparing a signal corresponding to one of the reference component and the signal component with a reference signal for conversion into digital data, and, concurrently with the comparison, counting in one of the down-count mode and the up-count mode based on a counter clock and holding a count value at a time of completion of the comparison;
• and
• in a second processing iteration, comparing the other one of the reference component and the signal component with the reference signal, and, concurrently with the comparison, counting in the other one of the down-count mode and the up-count mode and holding a count value at a time of completion of the comparison,
• wherein,
• the counter includes an initial-value setting processor that sets a count value immediately before switching of count mode as an initial value at a time of the switching of count mode before starting counting after the count mode is switched, and
• the timing controller controls the initial-value setting processor so that counting in a second processing iteration is started from a count value held in a first processing iteration.

An analog-to-digital converter for converting a difference signal component into digital data, the difference signal component representing a difference between a reference component and a signal component included in an analog signal subject to processing, the analog-to-digital converter comprising:

• a comparator that compares a signal corresponding to the reference component and a signal corresponding to the signal component with a reference signal for conversion into digital data;
• and
• an asynchronous counter that performs counting in a down-count mode or an up-count mode based on a counter clock, and concurrently with the comparison in the comparator, the counter holding a count value at a time of completion of the comparison in the comparator,
• wherein
• the counter includes a gate circuit that controls input of the count clock based on a comparison output supplied from the comparator,
• the counter includes an initial-value setting processor that sets a count value immediately before switching of count mode as an initial value at a time of the switching of count mode before starting counting after the count mode is switched, and
• the timing controller controls the initial-value setting processor so that counting in a second processing iteration is started from a count value held in a first processing iteration.

A semiconductor device for detecting a distribution of physical quantities, the semiconductor device including (a) a matrix of unit elements, each of the unit elements including a charge generator that generates charges corresponding to incident electromagnetic wave and (b) a unit-signal generator that generates an analog unit signal including a reference component and a signal component, the semiconductor device comprising:

• a comparator that compares a signal corresponding to the reference component and a signal corresponding to the signal component with a reference signal for generating digital data of the signal component;
• an asynchronous counter that performs counting in a down-count mode or an up-count mode based on a counter clock, concurrently with the comparison in the comparator, the counter holding a count value at a time of completion of the comparison in the comparator;
• and
• a timing controller that switches mode of counting in the counter according to whether the comparator is performing comparison for the reference component or the signal component,
• wherein,
• the counter includes an initial-value setting processor that sets a count value immediately before switching of count mode as an initial value at a time of the switching of count mode before starting counting after the count mode is switched, and
• the timing controller controls the initial-value setting processor so that counting in a second processing iteration is started from a count value held in a first processing iteration.

An electronic apparatus comprising:

• a reference-signal generator that generates a reference signal for converting a difference signal component into digital data, the difference signal component representing a difference between a reference component and a signal component included in an analog signal subject to processing;
• a comparator for comparing a signal corresponding to the reference component and a signal corresponding to the signal component with the reference signal generated by the reference-signal generator;
• an asynchronous counter that performs counting in a down-count mode or an up-count mode concurrently with the comparison in the comparator, the counter holding a count value at a time of completion of the comparison in the comparator;
• and
• a timing controller that switches mode of counting in the counter according to whether the comparator is performing comparison for the reference component or the signal component,
• wherein,
• the counter includes an initial-value setting processor that sets a count value immediately before switching of count mode as an initial value at a time of the switching of count mode before starting counting after the count mode is switched, and
• the timing controller controls the initial-value setting processor so that counting in a second processing iteration is started from a count value held in a first processing iteration.

A solid-state imaging device comprising:

• a pixel array that includes pixels arranged two-dimensionally, each of the pixels having a photoelectric conversion element;
• a reference-signal generator that generates a reference signal;
• a comparator that compares a reset signal from said pixel array with the reference signal, and also compares an image signal from said pixel array with the reference signal;
• and an asynchronous counter that performs counting in two modes of a down-count mode and an up-count mode;
• wherein said asynchronous counter performs counting in one of the two modes while said comparator compares the reset signal with the reference signal, and said asynchronous counter performs counting in the other of the two modes while said comparator compares the image signal with the reference signal.