Methods and structures of providing modular integrated circuits
AssigneeXilinx, Inc.
InventorVenu M. Kondapalli
Life of this patent
Estimating the term…
Abstract
Modular wafers and integrated circuits (ICs), and methods of manufacturing modular ICs. A modular wafer can be optionally divided in various ways to avoid defects while producing a variety of modular ICs. A modular wafer includes an array of element dice separated by a scribe area. The scribe area includes interconnect lines that extend across the scribe area between each adjacent pair of the element dice. Unused interconnect lines can be pulled to a known value using weak pullups or pulldowns. Modular ICs can be manufactured with interconnect lines between each pair of adjacent element dice, in which case a single mask set can be used to manufacture a family of programmable logic devices (PLDs).
Claims14
A modular integrated circuit (IC) wafer, comprising:
- an array comprising rows and columns of substantially similar element dice each comprising a programmable IC;
- a scribe area separating each row and each column of the element dice one from another, wherein the scribe area comprises interconnect lines extending across the scribe area between each adjacent pair of the element dice;
- and
- for each of the interconnect lines extending across the scribe area, a transistor situated at each end of the interconnect line and on each side of the scribe area, each of the transistors being coupled between an associated one of the interconnect lines and power high or ground, each of the transistors having a gate terminal connected to a programmable memory cell of the programmable IC.
A modular integrated circuit (IC), comprising:
- an array comprising rows and columns of substantially similar element dice each comprising a programmable IC, the array being manufactured as an integral physical unit optionally separable into the element dice;
- a scribe area separating each row and each column of the element dice one from another, wherein the scribe area comprises interconnect lines extending across the scribe area between each adjacent pair of the element dice;
- and
- for each of the interconnect lines extending across the scribe area, a transistor situated at each end of the interconnect line and on each side of the scribe area, each of the transistors being coupled between an associated one of the interconnect lines and power high or ground, each of the transistors having a gate terminal connected to a programmable memory cell of the programmable IC.
Dependencies are inferred from the claim text.