Electrostatic discharge protective circuit and semiconductor integrated circuit using the same

A semiconductor integrated circuit device comprising:

• an internal circuit to be protected from an ESD voltage connected between a first power source terminal to which a predetermined voltage is applied and a grounded second power source terminal to be energized;
• a first MOS device which is logically controlled by the internal circuit and which configures a buffer circuit in which one of a drain and a source of the first MOS device is connected to a data input/output terminal;
• an ESD protective circuit having a discharge path connected between the data input/output terminal and the second power source terminal and having a trigger terminal;
• and
• a trigger circuit connected between the other of the drain and the source of the first MOS device and the trigger terminal of the ESD protective circuit,
• wherein the first MOS device functions as the buffer circuit at a time of normal operation state when an ESD voltage is not applied, and when the ESD voltage is applied, the first MOS device makes a trigger current flow from the first MOS device to the ESD protective circuit via the trigger circuit.

An electrostatic discharge protective circuit comprising;

• a first node;
• a second node which is electrically isolated from the first node during a normal operation state when there is no ESD voltage across the first and the second nodes;
• a third node which is electrically isolated from the first node and the second node during the normal operation state, the normal operation state further characterized as having no ESD voltage across the first and the third nodes and the second and the third nodes;
• a first ESD protective circuit having a first discharge path which is connected between the first and second nodes;
• a second ESD protective circuit having a second discharge path which is connected between the first and third nodes;
• a third ESD protective circuit having a discharge path which is connected between the second and third nodes;
• first, second and third trigger circuits which are respectively connected to trigger terminals of the first, second and third ESD protective circuits;
• first and second MOS devices included in a circuit to be protected as constituents thereof and connected to the first and third nodes, wherein one of a source and a drain of the first MOS device and one of a source and a drain of the second MOS device are connected in common to the third node and to the trigger terminals of the first and the second ESD protective circuits, the other of the source and the drain of the second MOS device is connected to the third trigger terminal of the third ESD protective circuit, and wherein the first and second MOS devices function as a part of the circuit to be protected at the time of the normal operation state when an ESD voltage is not applied to the first and the third nodes, and when the ESD voltage is applied, supply trigger signals to the first and the third trigger circuits;
• and
• a third MOS device included inside the circuit to be protected, wherein one of a source and a drain being of the third MOS device is connected to the second node, and the other of the source and the drain being connected to the second MOS device.

A semiconductor integrated circuit device comprising:

• an internal circuit connected between first and second power source terminals;
• a data input/output terminal connected to the internal circuit;
• a first ESD protective circuit connected between the first power source terminal and the data input/output terminal;
• a second ESD protective circuit connected between the second power source terminal and the data input/output terminal, wherein the internal circuit comprises:
• a first trigger signal supplying circuit which includes a first MOS device connected between the first power source terminal and the first ESD protective circuit, and the first MOS device functions as a part of the internal circuit at a time of normal operation state when an ESD voltage is not applied, and when the ESD voltage is applied, supplies trigger signals to the first ESD protective circuit;
• and
• a second trigger signal supplying circuit which includes a second MOS device connected between the data input/output terminal and the second ESD protective circuit, and which functions as a part of the internal circuit at the time of normal operation state when the ESD voltage is not applied, and when the ESD voltage is applied, supplies trigger signals to the second ESD protective circuit;
• wherein the first trigger signal supplying circuit includes a third MOS device connected between the first MOS device and the trigger terminal of the first ESD protective circuit, the third MOS device being held in a non-conductive state when no ESD voltage is applied;
• and
• the second trigger signal supplying circuit includes a fourth MOS device connected between the second MOS device and the trigger terminal of the second ESD protective circuit, the fourth MOS device being held in a non-conductive state when no ESD voltage is applied.

An electrostatic discharge protective circuit comprising:

• an ESD protective circuit connected between a power source terminal having a predetermined electric potential and a grounding terminal;
• a circuit to be protected which is connected between the power source terminal and the grounding terminal;
• and
• a trigger signal supplying circuit including first and second MOS devices included in the circuit to be protected, wherein one of a drain and a source of the first MOS device is connected to the power source terminal, the other of the drain and the source of the first MOS device is connected to a trigger terminal of the ESD protective circuit via a source and a drain of the second MOS device, a gate of the second MOS device is connected to the power source terminal for maintaining the second MOS device in a non-conductive state when no ESD voltage is applied, and the MOS circuit functions as a part of the circuit to be protected when the ESD voltage is not applied to the power source terminal, and becomes conductive to allow a current flow when the ESD voltage is applied to the power source terminal, so that the trigger signal supplying circuit supplying the current to the ESD protective circuit as trigger signals.