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US 7,256,975 B2Granted
ESD protection circuit and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Hsun Wu, Jian-Hsing Lee, Shui-Hung Chen
Life of this patent
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Abstract
An electrostatic discharge (ESD) protection circuit and method thereof are presented. In some embodiments, a high voltage tolerant input/output circuit comprises an ESD detection circuit, a first first-type transistor, a first second-type transistor, and a second second-type transistor. The first first-type transistor and the first second-type transistor are coupled to a pad. The ESD detection circuit determines whether ESD occurs at the pad and, if so, couples the gates of the first and second second-type transistors to the second power rail.
Claims18
An electrostatic discharge (ESD) protection circuit, comprising:
- a first first-type transistor;
- a first second-type transistor;
- a second second-type transistor, wherein the drains of the first first-type and second-type transistors are coupled to a pad, wherein the source of the first second-type transistor is coupled to the drain of the second second-type transistor, wherein the source of the first first-type transistor is coupled to a first power rail, and the source of the second second-type transistor is coupled to a second power rail, and wherein, during normal operation, the gate of the first second-type transistor is coupled to the first power rail, and the gate of the second second-type transistor is controlled by a pre-driver;
- an ESD detection circuit configured to detect whether ESD occurs at the pad, the ESD detection circuit being further configured to equalize voltage levels of the gates of the first and second second-type transistors and the second power rail during ESD;
- a redundant circuit having a second first-type transistor, a third second-type transistor, and a fourth second-type transistor, wherein the drain of the second first-type transistor and the drain of the third second-type transistor are coupled to the pad, wherein the source of the third second-type transistor is coupled to the drain of the fourth second-type transistor, wherein the source of the second first-type transistor is coupled to the first power rail, wherein the source and the gate of the fourth second-type transistor are coupled to the second power rail, and wherein, during normal operation, the gate of the third second-type transistor is coupled to the first power rail;
- and
- an inverter circuit coupled to the ESD detection circuit, the inverter circuit configured to couple the gate of the first second-type transistor and the gate of the third second-type transistor to the second power rail.
4 more elements
An electrostatic discharge (ESD) protection circuit, comprising:
- a first first-type transistor;
- a first second-type transistor;
- a second second-type transistor, wherein the drains of the first first-type and second-type transistors are coupled to a pad, wherein the source of the first second-type transistor is coupled to the drain of the second second-type transistor, wherein the source of the first first-type transistor is coupled to a first power rail, and wherein the source of the second second-type transistor is coupled to a second power rail;
- an ESD detection circuit configured to detect whether ESD occurs at the pad;
- a first NOR gate controlled by the second power rail and a first signal, the first NOR gate configured to output a second signal at an output end thereof, wherein the logic levels of the second signal and the first signal are inverted;
- a first inverter circuit coupled to the first NOR gate, the first inverter circuit configured to receive the second signal and output a third signal, wherein the logic levels of the third signal and the second signal are inverted;
- a voltage shifter configured to receive the third signal, convert the voltage level of the third signal, and output a voltage conversion signal;
- a second NOR gate controlled by the ESD detection circuit and the voltage shifter, wherein, during normal operation, the second NOR gate controls the gate of the second second-type transistor according to the voltage conversion signal, and wherein, during ESD at the pad, the second NOR gate couples the gate of the second second-type transistor to the second power rail according to the ESD detection circuit;
- and
- a second inverter circuit coupled to the ESD detection circuit, the second inverter circuit configured to couple the gate of the first second-type transistor to the second power rail.
7 more elements
Dependencies are inferred from the claim text.