Ultra low dielectric constant integrated circuit system
AssigneeAdvanced Micro Devices, Inc.
InventorsLu You, Fei Wang, Minh Quoc Tran, Lynne A. Okada
Life of this patent
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Abstract
An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in the ultra-low dielectric constant dielectric layer and a barrier layer is deposited to line the dielectric liner and conductor core is deposited to fill the opening over the barrier layer.
Claims20
An integrated circuit system for manufacturing an integrated circuit system comprising:
- providing a semiconductor substrate having a semiconductor device provided thereon;
- forming a porous ultra-low dielectric constant dielectric layer over the semiconductor substrate;
- forming an opening in the ultra-low dielectric constant dielectric layer;
- forming a dielectric liner to line the opening in the ultra-low dielectric constant dielectric layer without contacting inner surfaces of pores in the ultra-low dielectric constant dielectric layer;
- depositing a barrier layer to line the dielectric liner;
- and
- depositing a conductor core over the barrier layer to fill the barrier layer and connect to the semiconductor device.
An integrated circuit system for manufacturing an integrated circuit system comprising:
- providing a semiconductor substrate having a semiconductor device provided thereon;
- depositing a porous ultra-low dielectric constant dielectric layer over the semiconductor substrate, depositing the ultra-low dielectric constant dielectric layer deposits a dielectric material having a dielectric constant under 2.5;
- forming an opening in the ultra-low dielectric constant dielectric layer;
- depositing a dielectric liner to line the opening in the ultra-low dielectric constant dielectric layer without contacting inner surfaces of pores in the ultra-low dielectric constant dielectric layer;
- depositing a barrier layer to line the dielectric liner;
- and
- depositing a conductor core over the barrier layer to fill the barrier layer and connect to the semiconductor device.
An integrated circuit system comprising:
- a semiconductor substrate having a semiconductor device provided thereon;
- a porous ultra-low dielectric constant dielectric layer over the semiconductor substrate having an opening provided therein;
- a dielectric liner lining the opening in the ultra-low dielectric constant dielectric layer without contacting the inner surfaces of pores in the ultra-low dielectric constant dielectric layer;
- a barrier layer lining the dielectric liner;
- and
- a conductor core over the barrier layer to fill the barrier layer and connect to the semiconductor device.
Dependencies are inferred from the claim text.