Antifuse element and electrically redundant antifuse array for controlled rupture location

A method of forming an antifuse element, the method comprising:

• providing a substrate material having an active area formed in an uppermost surface;
• forming a gate electrode having an outer perimeter end corner positioned above the active area;
• and
• forming an insulating layer disposed between the gate electrode and the active area such that a voltage between the gate electrode and the active area creates a current path through the insulating layer and an electric field at the outer perimeter end corner positioned above the active area, causing a rupture of the insulating layer at a point beneath the outer perimeter end corner of the gate electrode.

An electrically redundant antifuse array comprising:

• a plurality of antifuse elements formed on a substrate, each antifuse element comprising:
• an active area formed in an uppermost surface of the substrate;
• a gate electrode having an outer perimeter end corner positioned above the active area;
• and
• an insulating layer disposed between the gate electrode and the active area such that a voltage between the gate electrode and the active area creates a current path through the insulating layer and an electric field at the outer perimeter end corner positioned above the active area, causing a rupture of the insulating layer at a point beneath the outer perimeter end corner of the gate electrode.

An electrically redundant antifuse array comprising:

• a plurality of antifuse elements formed on a substrate, each antifuse element comprising:
• an active area formed in an uppermost surface of the substrate;
• a gate electrode having an end corner positioned above the active area;
• and
• an insulating layer disposed between the gate electrode and the active area such that a voltage between the gate electrode and the active area creates a current path through the insulating layer and an electric field at the end corner positioned above the active area, causing a rupture of the insulating layer at a point beneath the end corner of the gate electrode,
• wherein the plurality of antifuse elements are formed on opposing sides of an uppermost surface of the substrate, and including end corners of the plurality of gate electrodes interleaved.