Body-biased pMOS protection against electrostatic discharge

A protection circuit for protecting an integrated circuit pad against an ESD pulse, comprising:

• a discharge circuit including an elongated multifinger a p-type metal-oxide-semiconductor (PMOS) transistor formed on a substrate having a gate connected to said integrated circuit pad, said discharge circuit operable to discharge said ESD pulse to ground;
• a pump circuit comprising:
• an input for receiving a current portion of said ESD pulse;
• an n-type metal-oxide-semiconductor (NMOS) transistor for determining the size of said current portion, said NMOS transistor having its source connected to ground and its gate capacitively coupled to said integrated circuit pad;
• a discrete resistor connected between said input and said NMOS transistor, said resistor operable to generate a voltage drop corresponding to said current portion;
• and
• a plurality of contacts to said substrate connected to said resistor so that said voltage drop is uniformly impressed on said substrate to provide a substrate bias, wherein the substrate bias ensures uniform turn on of said elongated transistor for uniform pulse discharge.