NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
Estimating the term…
Abstract
A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of a nanolaminate structure. The NROM memory cell has a substrate with doped source/drain regions. The high-k gate dielectric is formed above the substrate. A polysilicon control gate is formed on top of the gate dielectric. The gate dielectric may have an oxide-high-k dielectric-oxide composite structure or an oxide-oxide-high-k dielectric composite structure.
Claims18
An NROM device comprising:
- a memory array having a plurality of NROM memory transistors arranged in a row and column format, each transistor comprising:
- a substrate having a plurality of source/drain regions, the source/drain regions having a different conductivity than the remainder of the substrate;
- a composite high-k-low-k-high-k nanolaminate gate insulator formed by oxidation of metals overlying the substrate and substantially between the plurality of source/drain regions;
- and
- a control gate formed on top of the gate insulator;
- wherein a thickness of at least one of the high-k layers of the gate insulator is controlled during the oxidation of metals to maintain an excess of metal in that high-k layer.
An electronic system comprising:
- a processor that generates control signals;
- and
- a memory device coupled to the processor, the device comprising a plurality of NROM memory cells, each NROM memory cell comprising:
- a substrate having a plurality of source/drain regions, the source/drain regions having a different conductivity type than the remainder of the substrate;
- a composite high-k-low-k-high-k nanolaminate gate insulator overlying the substrate wherein at least one high-k layer of the gate insulator is formed by an oxidation of metal, the high-k layers having a dielectric constant greater than a dielectric constant of silicon dioxide;
- and
- a control gate formed on top of the gate insulator;
- wherein a thickness of at least one of the high-k layers of the gate insulator is controlled during the oxidation of metal to maintain an excess of metal in that high-k layer.
An NROM memory transistor comprising:
- a substrate having a plurality of source/drain regions, the source/drain regions having a different conductivity type than the remainder of the substrate;
- a composite high-k-low-k-high-k nanolaminate gate insulator wherein at least one high-k layer is formed by an oxidation of metal overlying the substrate, a high dielectric constant is greater than a dielectric constant of silicon dioxide;
- and
- a control gate formed on top of the gate insulator;
- wherein a thickness of at least one of the high-k layers of the gate insulator is controlled during the oxidation of metal to maintain an excess of metal in that high-k layer.
A memory array comprising:
- a plurality of NROM memory transistors arranged in a row and column format, each transistor comprising:
- a substrate having a plurality of source/drain regions, the source/drain regions having a different conductivity than the remainder of the substrate;
- a composite high-k-low-k-high-k nanolaminate gate insulator formed by oxidation of metals overlying the substrate and substantially between the plurality of source/drain regions;
- and
- a control gate formed on top of the gate insulator;
- wherein a thickness of at least one of the high-k layers of the gate insulator is controlled during the oxidation of metals to maintain an excess of metal in that high-k layer.
Dependencies are inferred from the claim text.