Trench capacitor array having well contacting merged plate

A method of forming a structure including a plurality of trench capacitors arranged in an array, comprising:

• a substrate including a single-crystal semiconductor region;
• forming a plurality of trenches in the single-crystal semiconductor region, the plurality of trenches being arranged in an array including a first dummy trench of the plurality of trenches defining a first peripheral edge of the array, a second dummy trench of the plurality of trenches defining a second peripheral edge of the array remote from the first peripheral edge and a plurality of third trenches between the first and second dummy trenches, the array having a lateral dimension extending between the first and second peripheral edges;
• forming a plurality of trench capacitors including forming a continuous buried plate diffusion region in the single-crystal semiconductor region, the buried plate diffusion region having a lateral dimension equal to or larger than a lateral dimension of the array, and forming a node dielectric layer of each trench capacitor, the node dielectric layer extending along a wall of a trench of the plurality of trenches, the plurality of trench capacitors having node dielectric layers along walls of the third trenches having a first circuit function, and each of the trench capacitors having node dielectric layers along walls of the first and second dummy trenches not having the first circuit function;
• forming a structure embedded in the single-crystal semiconductor region, the structure including a doped well region and an isolation region, the isolation region overlying a portion of the buried plate diffusion region and overlying at least the first dummy trench, the isolation region not overlying the third trenches, the doped well region being laterally adjacent to the isolation region, the doped well region extending downwardly from a major surface of the single-crystal semiconductor region to a depth below a top level of the buried plate diffusion region at which the doped well region merges with the buried plate diffusion region;
• and
• forming a contact in conductive communication with the doped well region to provide a conductive path through the doped well region to the buried plate diffusion region, the buried plate diffusion region serving as a common capacitor plate belonging to all of the plurality of trench capacitors.