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US 7,256,089 B2Granted
Top electrode barrier for on-chip die de-coupling capacitor and method of making same
AssigneeIntel Corporation
InventorsRichard Scott List, Bruce A. Block, Ruitao Zhang
Life of this patent
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Abstract
An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.
Claims7
A method comprising:
- providing an integrated circuit having a layer of metal;
- forming an on-chip decoupling capacitor stack, the on-chip decoupling capacitor stack including,
- a bottom electrode on the layer of metal;
- a dielectric layer;
- a top electrode separated from the bottom electrode by the dielectric layer;
- and
- a conductive top electrode barrier contacting the top electrode,
- wherein the top electrode barrier comprises a material that is more electrically conductive than a material for the top electrode, and
- wherein the top capacitor electrode is formed on the dielectric layer and the top electrode barrier is formed on the top electrode in a single deposition chamber without removing the on-chip decoupling capacitor stack from the single deposition chamber.
6 more elements
A method comprising:
- providing an integrated circuit with a layer of metal;
- planarizing the layer of metal;
- depositing a blanket bottom electrode material over the layer of metal;
- depositing a dielectric material having a dielectric constant of greater than about 7;
- depositing a blanket top electrode material separated from the bottom electrode material by the dielectric material;
- depositing a blanket top electrode barrier;
- patterning the dielectric material, top electrode material and top electrode barrier into a capacitor stack;
- depositing a blanket passivation layer;
- and
- wherein depositing the top electrode barrier comprises depositing a material that is more electrically conductive than a material for the top electrode, and
- wherein the top electrode is deposited on the dielectric layer and the top electrode barrier is deposited on the top electrode in a single deposition chamber without removing the on-chip decoupling capacitor stack from the single deposition chamber.
8 more elements
Dependencies are inferred from the claim text.