Composite stress spacer
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsKhee Yong Lim, Wenhe Lin, Chung Woh Lai, Yong Meng Lee, Liang Choo Hsia, Young Way Teh, John Sudijono, Wee Leng Tan, Hui Peng Koh
Life of this patent
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Abstract
An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.
Claims19
A method of fabrication of a semiconductor device structure comprising the steps of:
- a) providing a substrate having a PFET region and a NFET region, a PFET gate over said PFET region, and a NFET gate over said NFET region;
- said PFET gate having PFET gate sidewalls;
- said NFET gate having NFET gate sidewalls;
- b) forming NFET source/drain regions adjacent to said NFET gate;
- then
- c) forming tensile PFET spacers over the PFET gate sidewalls and tensile NFET spacers over the NFET gate sidewalls;
- d) implanting first ions into the tensile PFET spacers to form neutralized PFET spacers whereby the first ions reduce a stress in the neutralized PFET spacers and reduce a stress in the PFET region;
- and
- e) forming PFET source/drain regions adjacent to said PFET gate.
A method of fabrication of semiconductor device structure comprising the steps of:
- a) providing a substrate having a PFET region and a NFET region, a nwell region in said PFET region, a PFET gate over said PFET region, and a NFET gate over said NFET region;
- said PFET gate having PFET gate sidewalls;
- said NFET gate having NFET gate sidewalls;
- b) forming first PFET spacers over said PFET gate sidewalls and forming first NFET spacers over said NFET gate sidewalls;
- c) forming NFET source/drain regions adjacent to said first NFET spacers;
- d) removing said first PFET spacers and said first NFET spacers;
- e) forming tensile PFET spacers over the PFET gate sidewalls and tensile NFET spacers over the NFET gate sidewalls;
- (1) the tensile PFET spacers and the tensile NFET spacers have a tensile stress between 8 Gdynes/cm2 and 16 Gdynes/cm2;
- f) implanting first ions into the tensile PFET spacers to form neutralized PFET spacers and into said PFET region whereby the first ions relax a stress in the neutralized PFET spacers and a stress in the PFET region;
- (1) the neutralized PFET spacers have a tensile stress between about 2 Gdynes/cm2 and 4 Gdynes/cm2 after the first ion implant;
- (2) said first ions are Ge or Xe ions;
- and
- (g) implanting P type impurities into said PFET region to form PFET source/drain regions adjacent to said neutralized PFET spacers.
A method of fabrication of a semiconductor device structure comprising the steps of:
- a) providing a substrate having a PFET region and a NFET region, a PFET gate over said PFET region, and a NFET gate over said NFET region;
- said PFET gate having PFET gate sidewalls;
- said NFET gate having NFET gate sidewalls;
- b) forming first PFET spacers over said PFET gate sidewalls and forming first NFET spacers over said NFET gate sidewalls;
- c) forming NFET source/drain regions adjacent to said first NFET spacers;
- then
- d) removing said first PFET spacers and said first NFET spacers;
- e) forming tensile PFET spacers over the PFET gate sidewalls and forming tensile NFET spacers over the NFET gate sidewalls;
- f) implanting first ions into the tensile PFET spacers to form neutralized PFET spacers whereby the first ions reduce a stress in the neutralized PFET spacers and reduce a stress in the PFET region;
- and
- g) forming PFET source/drain regions adjacent to said PFET gate.
Dependencies are inferred from the claim text.