On-chip latch-up protection circuit

#This nonprovisional application claims priority under 35 U.S.C. § 119(a) on patent application Ser. No(s). 091,111,475 filed in TAIWAN, R.O.C. on May 29, 2002, which is(are) herein incorporated by reference.

#1. Field of the Invention

#The present invention relates in general to an on-chip latch-up protection circuit. In particular, the present invention relates to an on-chip latch-up protection circuit detecting and terminating a latch-up.

#The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention, and in which:

#FIG. 1A is a block diagram of the first embodiment of an on-chip latch-up protection circuit according to the present invention;

#FIG. 1B is a circuit to implement the block diagram in FIG. 1A;

#The First Embodiment

#FIG. 1A is a block diagram of the first embodiment of an on-chip latch-up protection circuit according to the present invention. A power switch 10, a core circuit 12 and a current extractor 14 are sequentially coupled in series between a high power line VDD and a low power line VSS. The core circuit 12 can be CMOS circuits excluding those of input/output (I/O) ports and is generally located at the center of a chip carrying out logic or analogue process. Total current flowing through the core circuit 12 is named major current. A great part of the major current flows through the power switch 10 and the current extractor 14 coupled in series with the core circuit 12.

#The current extractor 14 is used to detect amplitude of the major current. When the major current surpasses a predetermined amplitude, the power switch 10 is turned off by the current extractor 14 to become an open circuit. The major current is then blocked or decreased to almost zero. As a result, the major current flowing through the core circuit 12 is too small for latch-up to persist. The predetermined amplitude of the major current varies according to the variety of the core circuit 12 and is used as a reference for distinguishing a latch-up event from normal operations.