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US 7,253,486 B2Granted
Field plate transistor with reduced field plate resistance
AssigneeFreescale Semiconductor, Inc.
InventorsBruce M. Green, Ellen Lan, Phillip Li
Life of this patent
Estimating the term…
Abstract
In one example embodiment, a transistor (100) is provided. The transistor (100) comprises a source (10), a gate (30), a drain (20), and a field plate (40) located between the gate (30) and the drain (20). The field plate (40) comprises a plurality of connection locations (47) and a plurality of electrical connectors (45) connecting said plurality of connection locations (47) to a potential.
Claims20
A transistor, the transistor comprising:
- a source;
- a gate;
- a drain;
- a field plate located between the gate and the drain,
- wherein said field plate comprises a plurality of connection locations;
- and
- a plurality of electrical connectors connecting said plurality of connection locations to a potential.
4 more elements
A system for reduction of gate-to-drain capacitance in a transistor, the system comprising:
- means for connecting a plurality of locations on a field plate finger to a potential, the field plate finger being located between a drain of a transistor and a source of the transistor;
- and
- means for applying a voltage to the means for connecting.
Dependencies are inferred from the claim text.