Semiconductor device layout and channeling implant process
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsYisuo Li, Xiaohong Jiang, Francis Benistant
Life of this patent
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Abstract
A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.
Claims23
A semiconductor device comprised of at least one field effect transistor (FET) having a source, drain and gate with the source and drain separated by a channel under the gate, comprising:
- a {001} silicon substrate;
- a gate having a gate length and a gate width;
- said gate having the gate width in the [100] or [010] crystal directions;
- a source on one side of said gate and a drain on the other side of the gate, with impurities of the source and drain being disposed in the {001} silicon substrate;
- and
- a channel under the gate between the source and drain when voltage is applied and being aligned in a direction parallel with the direction of the gate width, whereby the performance of the FET is enhanced.
An integrated circuit with at least one field effect transistor (FET) having a source, drain and gate with the source and drain separated by a channel under the gate, comprising:
- a {001} monocrystalline silicon substrate having (100) and (110) crystal planes and [100] and [110] crystal directions;
- a gate having a length and a width and being insulated from the substrate by a gate dielectric layer, said gate having a gate width in the [100] or [010] crystal direction;
- a source on one side of the gate width and a drain on the other side of the gate width, and
- a channel being formed under the gate between the source and drain when voltage is applied and being aligned in a direction parallel with the direction of the gate width.
A semiconductor device comprised of at least one field effect transistor (FET) having a source, drain and gate with the source and drain separated by a channel under the gate, comprising:
- a {001} silicon substrate;
- a gate comprised of a first gate portion;
- said first gate portion having a first gate portion length and a first gate portion width;
- said first gate portion width in the [100] or [010] crystal directions;
- a source on one side of said gate and a drain on the other side of the gate, with impurities of the source and drain being disposed in the {001} silicon substrate;
- and
- a first channel region under the first gate portion between the source and drain;
- the first channel region and aligned in a direction parallel with [100] or [010] crystal directions, whereby the performance of the FET is enhanced.
Dependencies are inferred from the claim text.