US 7,253,112 B2 · Dual damascene process

Abstract

A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

Claims20

Dependent claims

A method, for fabricating inlaid interconnect wiring and contact vias in integrated circuits using a dual damascene process, comprising:

providing a substrate;
forming an interlevel dielectric layer over the substrate;
patterning the interlevel dielectric layer forming via openings;
completely filling a plug material in each via opening, such that the upper surface of the interlevel dielectric layer is substantially planar with the plug material;
coating a bottom anti-reflective coating over the interlevel dielectric layer and the plug material;
etching the bottom anti-reflective coating, the underlying interlevel dielectric layer and the plug material, thereby forming a trench opening over each via opening and removing the plug material therein;
and
filling the trench/via openings with conducting metal forming the inlaid conducting interconnect wiring and contact vias.

5 more elements

Dependencies are inferred from the claim text.

Dual damascene process

Life of this patent

Dual damascene process

Life of this patent

Abstract

Claims20