Method for forming 1 TRAM cell and structure formed thereby
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChung-Cheng Chou
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Abstract
A single transistor random access memory cell has an MOS well, a transfer gate of the transistor and a storage capacitor having a storage node in the well that becomes an inversion layer at a threshold voltage near zero. The inversion layer diffuses to an inversion region beneath the transfer gate when the transfer gate is turned on. For high speed operation, a doped region beneath the transfer gate becomes an inversion layer at a threshold voltage near zero. In this invention, a storage node junction is removed, which removes junction leakage and reduces subthreshold leakage current significantly.
Claims14
A single transistor random access memory cell, comprising:
- a transfer gate over a substrate having a recess;
- a storage capacitor having a capacitor plate horizontally adjacent to the transfer gate;
- and
- a shallow trench isolation, STI, insulator within the recess of the substrate, the STI insulator having a height smaller than a depth of the recess of the substrate, wherein the
- a capacitor plate covers the STI insulator and conformally covers a sidewall of the recess of the substrate.
Dependencies are inferred from the claim text.