Method for planarizing semiconductor structures

A method for forming one or more isolation structures on a semiconductor substrate, comprising:

• forming a first dielectric layer having one or more openings on the semiconductor substrate;
• etching the semiconductor substrate through the openings to form one or more trenches in a first pattern density in a first area of the semiconductor substrate, and one or more trenches in a second pattern density in a second area of the semiconductor substrate, wherein the second pattern density is lower than the first pattern density;
• forming a second dielectric layer on the first dielectric layer, and covering the trenches in the first and second areas;
• performing a first chemical mechanical polishing on the second dielectric layer using a predetermined type of slurry for reducing a thickness thereof;
• rinsing the second dielectric layer using deionized water;
• and
• performing a second chemical mechanical polishing on the second dielectric layer using the predetermined type of slurry for further removing the second dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas, and
• wherein the predetermined type of slurry provides a higher polish rate for the second dielectric layer than the first dielectric layer.

A method for forming one or more isolation structures on a semiconductor substrate, comprising:

• forming a silicon nitride layer having one or more openings on the semiconductor substrate;
• etching the semiconductor substrate through the openings to form one or more trenches in a first pattern density in a first area of the semiconductor substrate, and one or more trenches in a second pattern density in a second area of the semiconductor substrate wherein the second pattern density is lower than the first pattern density;
• forming a silicon oxide layer on the silicon nitride layer, and covering the trenches in the first and second areas;
• performing a first chemical mechanical polishing on the silicon oxide layer using a predetermined type of slurry providing a higher polish rate for the silicon oxide layer than the silicon nitride layer for reducing a thickness of the silicon oxide layer;
• rinsing;
• the silicon oxide layer using deionized water;
• and
• performing a second chemical mechanical polishing on the silicon oxide layer using the predetermined type of slurry for removing the silicon oxide layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.

A method for planarizing a semiconductor structure, comprising:

• providing a semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density;
• forming a first dielectric layer comprising silicon nitride and a second dielectric layer, the second dielectric layer covering the trenches in the first and second areas and the first dielectric layer;
• performing a first chemical mechanical polishing on the second dielectric layer using a predetermined type of slurry for reducing a thickness thereof;
• rinsing the polished second dielectric layer by using deionized water;
• and
• performing a second chemical mechanical polishing on the second dielectric layer using the predetermined type of slurry for removing the second dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas, and
• wherein the predetermined type of slurry provides a higher polish rate for the second dielectric layer than the first dielectric layer.