Selective deposition of double damascene metal
AssigneeGary Neal Poovey
InventorsSamuel Kinner, Gary Poovey
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Abstract
A method has been disclosed that allows the selective deposition of the metal for double damascene silicon wafer processing. This selective deposition allows the metal to be deposited only in the via holes, contact holes, channels or where ever the deposition is targeted to be deposited on the wafer where it is needed. This method allows double damascene wafers to be processed with out the necessity of polishing back the whole surface of the wafer to remove metal from most of the wafer surface, as is currently the practice.
Claims9
A process for deposition of copper on semiconductor wafers that selectively deposits metal only on the surfaces that the metal will remain involving the steps of:
- using a conductive photo resist mask to pattern an insulating layer that is etched for metal lines to be patterned is left on the wafer;
- attaching a positive electrical lead to the photo resist mask that patterns the insulating layer so that little or no metal will be deposited where the photo resist mask is present;
- attaching a negative electrical lead to the wafer so that the metal deposition only occurs in an electro plating bath in via holes, contact holes, channels or other targeted areas for electrical connection of devices;
- immersing the wafer in the metal electroplating bath;
- taking wafer out of the metal electroplating bath once the desired thickness of metal is deposited;
- and
- removing the photo resist mask.
Dependencies are inferred from the claim text.