US 7,247,555 B2 · Method to control dual damascene trench etch profile and trench depth uniformity

Abstract

A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. Via first patterning in dual damascene processing is one of the major integration schemes for copper backend of line (BEOL) integration. Via first dual damascene scheme usually uses a hard mask layer deposited on top of an inter-metal dielectric (IMD) film stack. The dual damascene trench etch requires uniform trench depth across wafer after etch. In addition, via top corner profiles need to be well maintained without any fencing or faceting. The present method solves these problems by using a two component hard mask layer, termed a bi-layer, deposited directly on top of an inter-metal dielectric (IMD) film stack.

Claims30

Dependent claims

A method for fabricating IC's comprising the following steps:

(a) providing a substrate with an insulating layer over the substrate;
(b) providing a first level of conducting material defined and embedded in the insulating layer over the substrate;
(c) depositing an intermetal dielectric layer over the insulating layer;
(d) forming a bi-layered hard mask over the intermetal dielectric layer, the bi-layered hard mask comprising a first hard mask layer HM1 overlying a second hard mask layer HM2;
(e) patterning the intermetal dielectric layer and hard mask layers, and CF4/N2/O2 based reactive ion etching to form via openings extending through the intermetal dielectric layer and one of the hard mask layers;
(f) forming a layer of via-fill material of bottom anti-reflective coating with photoresist over the intermetal dielectric layer, the via-fill material filling the via openings;
(g) patterning the via-fill material, intermetal dielectric layer and hard mask layers, and etching to form trench openings using a reactive ion etch;
and
(h) stripping-off the via-fill material after forming the trench openings, thus forming open trench and open via regions for subsequent conducting metal fill.

6 more elements

A method of fabricating an integrated circuit with a dual damascene process using a bi-layer hard mask, the method comprising the following steps:

(a) providing a substrate with an insulating layer over the substrate;
(b) providing a first level of conducting material defined and embedded in the insulating layer over the substrate;
(c) depositing an intermetal dielectric layer over the insulating layer;
(d) forming a bi-layered hard mask, two hard mask layers, over the intermetal dielectric layer, the bi-layered hard mask comprising a first hard mask layer HM1 overlying a second hard mask layer HM2;
(e) patterning the intermetal dielectric layer and hard mask layers, and CF4/N2/O2 based reactive ion etching to form via openings extending through the intermetal dielectric layer and one of the hard mask layers;
(f) forming a layer of via-fill material of bottom anti-reflective coating with photoresist over the intermetal dielectric layer, the via-fill material filling the via openings;
(g) patterning the via-fill material, intermetal dielectric layer and hard mask layers, and etching to form trench openings using a reactive ion etch;
(h) stripping-off the via-fill material after forming the trench openings, forming open trench and open via regions;
(i) depositing a copper seed layer in the trench openings and via openings;
(j) forming an excess of copper metal over the copper seed layer;
and
(k) planarizing the excess copper back, thus forming inlaid copper in the trench and via openings for contact vias and interconnect wiring.

9 more elements

A method of fabricating an integrated circuit with a dual damascene process for applications in MOSFET CMOS memory and logic devices, using a bi-layer hard mask, the method comprising the following steps:

(a) providing a substrate with an insulating layer over the substrate;
(b) providing a first level of conducting material defined and embedded in the insulating layer over the substrate;
(c) depositing an intermetal dielectric layer over the insulating layer;
(d) forming a bi-layered hard mask, two hard mask layers, over the intermetal dielectric layer, the bi-layered hard mask comprising a first hard mask layer HM1 overlying a second hard mask layer HM2;
(e) patterning the intermetal dielectric layer and hard mask layers, and CF4/N2/O2 based reactive ion etching to form via openings extending through the intermetal dielectric layer and one of the hard mask layers;
(f) forming a layer of via-fill material of bottom anti-reflective coating with photoresist over the intermetal dielectric layer, the via-fill material filling the via openings;
(g) patterning the via-fill material, intermetal dielectric layer and hard mask layers, and etching to form trench openings using a reactive ion etch;
(h) stripping-off the via-fill material after forming the trench openings, forming open trench and open via regions;
(i) depositing a copper seed layer in the trench openings and via openings;
(j) forming an excess of copper metal over the copper seed layer;
and
(k) planarizing the excess copper back, thus forming inlaid copper in the trench and via openings for contact vies and interconnect wiring.

9 more elements

Dependencies are inferred from the claim text.

Method to control dual damascene trench etch profile and trench depth uniformity

Life of this patent

Method to control dual damascene trench etch profile and trench depth uniformity

Life of this patent

Abstract

Claims30