Decoupling capacitor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJiaw-Ren Shih, Jian-Hsing Lee, Shui-Hung Chen
Life of this patent
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Abstract
A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.
Claims2
A method for fabricating a decoupling capacitor with increased resistance to electrostatic discharges on an integrated circuit, the method comprising:
- forming a well region in a substrate;
- forming a gate oxide layer above the well region;
- forming a polysilicon gate structure above the gate oxide layer;
- forming a source region proximate to the gate oxide layer;
- forming a drain region proximate to the gate oxide layer and opposite the source region;
- forming a first node in the well region of a conductivity type opposite to that of the source region;
- forming a second node in the substrate of a conductivity type opposite to that of the first node;
- covering the polysilicon gate structure, the source region, the drain region, and the first and second nodes with a dielectric layer;
- and
- forming, through the dielectric layer, a first interconnection to the source region and a second interconnection to the polysilicon gate structure, while leaving the dielectric layer above the drain region intact, wherein the drain region is not connected to an interconnection and is floating;
- forming another polysilicon gate structure for a second decoupling capacitor;
- and
- connecting the polysilicon gates with a polysilicon line, so that the two decoupling capacitors are combined into a single decoupling capacitor.
Dependencies are inferred from the claim text.