US 7,247,528 B2 · Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques

Abstract

Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

Claims33

Dependent claims

A method of fabricating a semiconductor integrated circuit, the method comprising:

forming an inter-layer insulating layer on a single-crystalline semiconductor substrate;
forming a single-crystalline semiconductor plug penetrating the inter-layer insulating layer;
forming a single-crystalline epitaxial semiconductor pattern covering the inter-layer insulating layer, the single-crystalline epitaxial semiconductor pattern being in contact with the single-crystalline semiconductor plug;
at least partially planarizing the single-crystalline epitaxial semiconductor pattern to form a semiconductor body layer on the inter-layer insulating layer;
and
patterning the semiconductor body layer to form a semiconductor body.

3 more elements

A method of fabricating a thin film transistor static random access memory (TFT SRAM) cell composed of first and second half-cells, the method of fabricating one of the first and second half-cells comprising:

forming an isolation layer on a predetermined region of a single-crystalline semiconductor substrate to define an active region;
forming a driver transistor at the active region, the driver transistor having a driver gate electrode extending across the active region and source/drain regions located on both sides of a channel region below the driver gate electrode;
forming an inter-layer insulating layer overlying the driver transistor;
forming a single-crystalline semiconductor plug penetrating the inter-layer insulating layer to contact the drain region of the driver transistor;
forming a single-crystalline epitaxial semiconductor pattern covering the inter-layer insulating layer, the single-crystalline epitaxial semiconductor pattern being in contact with the single-crystalline semiconductor plug;
planarizing the single-crystalline epitaxial semiconductor pattern to form a semiconductor body layer on the inter-layer insulating layer;
and
patterning the semiconductor body layer to form a semiconductor body.

5 more elements

Dependencies are inferred from the claim text.

Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques

Life of this patent

Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques

Life of this patent

Abstract

Claims33