US 7,235,424 B2 · Method and apparatus for enhanced CMP planarization using surrounded dummy design

Abstract

In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

Claims16

Dependent claims

A method for generating dummy pattern to eliminate film pattern density mismatch, the method comprising:

providing a substrate having a layout pattern density distribution thereon, the layout pattern density distribution defined by at least one interconnect on the surface of the substrate;
defining a first fill pattern having a plurality of small dummy fills, the first fill pattern defining an array of small dummy fills corrugating a trace along the interconnect;
identifying an extended region on the surface of the substrate, the extended region excluding the small dummy fills and the interconnect;
defining a second fill pattern, the second fill pattern having at least one large dummy fill covering a portion of the extended region;
wherein the second fill pattern defines an array independent of an array formed by the first fill pattern.

2 more elements

Dependencies are inferred from the claim text.

Method and apparatus for enhanced CMP planarization using surrounded dummy design

Life of this patent

Method and apparatus for enhanced CMP planarization using surrounded dummy design

Life of this patent

Abstract

Claims16