Differential amplifier circuit capable of accurately amplifying even high-speeded signal of small amplitude

A semiconductor integrated circuit device having a differential amplifier circuit receiving a differential signal, a latch circuit latching an output signal of said differential amplifier circuit, and a clock source generating a clock signal and supplying the generated clock signal to said differential amplifier circuit, wherein said differential amplifier circuit comprises a latch unit and a differential input portion, wherein:

• said differential input portion comprises a first transistor and a second transistor each having a first electrode, a second electrode and a control electrode;
• the control electrodes of said first and second transistors are supplied with the differential input signal;
• a third transistor is inserted between a first power line and a common node to which the first electrodes of said first and second transistors are connected, said third transistor keeps a minute current flowing through said first and second transistors in response to the clock signal at a first level, said third transistor supplies a first drive current, in response to the clock signal at a second level, said drive current through said third transistor is larger than said minute current;
• a fourth transistor is inserted between said first power line and the common node to which the first electrodes of said first and second transistors are connected, said fourth transistor supplying a second drive current in response to the clock signal at the second level;
• and
• said third transistor is connected in parallel to said fourth transistor.

A circuit device comprising:

• a transmission circuit outputting a differential signal;
• a signal transmission path;
• and
• a receiving circuit receiving the differential signal through said signal transmission path, wherein
• the receiving circuit comprises a plurality of receiving units, said plurality of receiving units carrying out an interleave operation, and wherein
• each of the plurality of receiving units comprises:
• a differential amplifier circuit receiving an Inter-Symbol Interference removed differential signal, a latch circuit latching an output signal of said differential amplifier circuit, and a clock source generating a clock signal and supplying the clock signal to said differential amplifier circuit, wherein said differential amplifier circuit comprises a latch unit and a differential input portion, wherein:
• said differential input portion comprises a first transistor and a second transistor each having a first electrode, a second electrode and a control electrode;
• the control electrodes of said first and second transistors are supplied with the Inter-Symbol Interference removed differential input signal;
• a third transistor for keeping a minute current to flow through said first and second transistors is inserted between a first power line and a common node to which the first electrodes of said first and second transistors are connected in response to a first level of the clock signal, wherein said third transistor supplies a drive current in response to a second level of the clock signal at the time of signal determination in said differential amplifier circuit;
• and
• an equalizer circuit, receiving the differential signal, removing an Inter-Symbol Interference of the differential signal by a Partial Response Detection, and outputting the Inter-Symbol Interference removed differential signal to said differential amplifier circuit.

A receiving circuit of a signal transmission system, said signal transmission system comprising a transmission circuit outputting a differential signal, a signal transmission path, and said receiving circuit receiving the differential signal through said signal transmission path, the receiving circuit comprising a receiving unit, wherein the receiving unit comprises:

• a differential amplifier circuit, said differential amplifier circuit including a latch unit and a differential input portion, wherein a minute current is kept to flow through said differential input portion;
• a latch circuit latching an output signal of said differential amplifier circuit;
• a clock source generating a clock and supplying the generated clock to said differential amplifier circuit;
• and
• an equalizer circuit for receiving the differential signal, removing an Inter-Symbol Interference of the differential signal by a Partial Response Detection, and outputting the Inter-Symbol Interference removed differential signal to said differential amplifier circuit.

A differential amplifier circuit comprising a latch unit and a differential input portion, wherein:

• said differential input portion comprises a first transistor and a second transistor each having a first electrode, a second electrode and a control electrode;
• the control electrodes of said first and second transistors are supplied with a differential input signal;
• a third transistor is inserted between a first power line and a common node to which the first electrodes of said first and second transistors are connected, a gate electrode of said third transistor receives a control signal of which level is changed in accordance with the operation of said differential amplifier circuit, said third transistor keeps a minute current flowing through said first and second transistors, in response to said control signal at a first level, said third transistor supplies a first drive current, in response to said control signal at a second level, said first drive current through said third transistor is larger than said minute current;
• and
• an eighth transistor inserted between a second power line and the common node to which the first electrodes of said first and second transistors are connected, the control electrode of said eighth transistor being supplied with clock signal.

A semiconductor integrated circuit device having a differential amplifier circuit receiving a differential signal, a latch circuit latching an output signal of said differential amplifier circuit, and a clock source generating a clock and supplying the generated clock to said differential amplifier circuit, wherein said differential amplifier circuit comprises a latch unit and a differential input portion, wherein:

• said differential input portion comprises a first transistor and a second transistor each having a first electrode, a second electrode and a control electrode;
• the control electrodes of said first and second transistors are supplied with the differential input signal;
• a third transistor is inserted between a first power line and a common node to which the first electrodes of said first and second transistors are connected, a gate electrode of said third transistor receives a control signal of which level is changed in accordance with the operation of said differential amplifier circuit, said third transistor keeps a minute current flowing through said first and second transistors in response to said control signal at a first level, said third transistor supplies a first drive current in response to said control signal at a second level, said first drive current through said third transistor is larger than said minute current;
• and
• an eighth transistor inserted between a second power line and the common node to which the first electrodes of said first and second transistors are connected, the control electrode of said eighth transistor being supplied with a clock signal.