Circuit for high-resolution phase detection in a digital RF processor

A time-to-digital converter (TOG) with on-line self calibration, comprising:

• a time-to-digital converter (TOG), comprising:
• an edge aligner adapted to compensate for any phase difference between complementary high speed clocks input thereto;
• a complementary chain of inverters coupled to the output of said edge aligner and operative to generate a delayed clock replica vector of said input complementary high speed clocks:
• a plurality of differential flip-flops coupled to said complementary chain of inverters and operative to sample said delayed clock replica vector in accordance with a frequency reference clock;
• and
• a self calibration circuit operative to receive the output of said plurality of differential flip-flops and to generate an inverter delay indicator therefrom.

A radio frequency (RF) frequency synthesizer for performing frequency modulation, comprising:

• a time-to-digital converter (TDC), comprising:
• an edge aligner adapted to compensate for any phase difference between complementary high speed docks input thereto;
• a complementary chain of inverters coupled to the output of said edge aligner and operative to generate a delayed clock replica vector of said input complementary high speed clocks;
• a plurality of differential flip-flops coupled to said complementary chain of inverters and operative to sample said delayed clock replica vector in accordance with a frequency reference clock;
• and
• a digitally controlled oscillator (DCO) operative to generate an output frequency in accordance with the phase error output from said TDC.

A time-to-digital converter (TDC) system for generating an output timestamp, comprising:

• a TDC operative to measure edge time d&ay from a high speed phase locked loop (PLL) clock to a reference frequency clock;
• a normalizer operative to normalize the delay output of said TOG to a period of said high speed PLL clock to generate a fractional portion of said output timestamp;
• and
• a counter operative to count edges of said high speed PLL clock and to generate an integer portion of said output timestamp.

A time-to-digital converter (TDC), comprising

• a converter for transforming single ended clock input into complementary high speed Clock signals;
• an edge Signer adapted to compensate for phase differences between said complementary high speed docks;
• a complementary chain of inverters coupled to the output of said edge aligner and operative to generate a delayed dock vector of said input complementary high speed docks;
• and
• a plurality of complementary flip-flops coupled to said complementary chain of inverters and operative to sample said delayed clock vector in accordance with a frequency reference clock.