Back to results
US 7,188,282 B2Granted
Tamper resistant shadow memory
AssigneeSilverbrook Research Pty Ltd
InventorSimon Robert Walmsley
Life of this patent
Estimating the term…
Abstract
An integrated circuit comprising a processor and memory, the memory storing a set of data representing program code and/or an operating value, wherein each bit of the data is stored as a bit/inverse-bit pair in corresponding pairs of physically adjacent bit cells in the memory.
Claims19
An integrated circuit comprising a processor and memory, the memory storing a set of data representing program code and/or an operating value, wherein each bit of the data is stored as a bit/inverse-bit pair in corresponding pairs of physically adjacent bit cells in the memory.
Dependencies are inferred from the claim text.