Shallow trench isolation using low dielectric constant insulator
AssigneeMicron Technology, Inc.
InventorsKlaus F. Schuegraf, Aftab Ahmad
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Abstract
A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.
Claims18
A trench isolation structure within a semiconductor substrate comprising:
- a trench in the semiconductor substrate;
- a halide-doped silicon dioxide region within the trench such that the region is completely recessed within the semiconductor substrate, wherein said halide-doped silicon dioxide region has a dielectric constant lower than the dielectric constant of silicon dioxide;
- and
- a barrier layer between at least a portion of said halide-doped silicon dioxide region and the semiconductor substrate, the barrier layer comprising a material that prevents halide migration from the halide-doped silicon dioxide region across the barrier layer into the semiconductor substrate.
A silicon semiconductor substrate comprising one or more trench isolation structures, wherein said one or more isolation structures comprise a halide-doped silicon dioxide isolation region within a trench in the semiconductor substrate, wherein said halide-doped isolation region has a height to width ratio of greater than 1 to 1, and wherein the top surface of said semiconductor substrate and the top of said one or more isolation structures is planar.
Dependencies are inferred from the claim text.