Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling

A multi-layer semiconductor wafer structure defining a multiplicity of dies formed thereon, said wafer structure comprising:

• a first scribe line having a selected width extending along a first direction;
• a second scribe line having a selected width extending along a second direction and intersecting said first scribe line;
• four dies located at and separated by the intersection of said first and second scribe lines wherein each of the four dies comprises a corner point adjacent the intersection of said first and second scribe lines;
• a first free area A1 on the first scribe line adjacent the corner point of the first die, wherein A1 is defined by the equation A1=D1×S1, and wherein D1 is the distance extending from the corner point of the first die, and S1 is the width of the first scribe line;
• a second free area A2 on the second scribe line adjacent the corner point of the second die, wherein A2 is defined by the equation A2=D2×S2, and wherein D2 is the distance from the corner point of the second die, and S2 is the width of the second scribe line;
• a third free area A3 on the second scribe line adjacent the third corner point of the third die, wherein A3 is defined by the equation A3=D3×S2, and wherein D3 is the distance from the corner point of the third die;
• a fourth free area A4 on the first scribe line adjacent the corner point of the fourth die, wherein A4 is defined by the equation A4=D4×S1, and wherein D4 is the distance from the corner point of the fourth die;
• and
• a fifth free area AS on the intersection of the first scribe line and the second scribe line and is defined by the equation AS=S1×S2.