Distributed capacitor array

A method for forming a capacitor structure in an integrated circuit, comprising the steps of:

• providing a semiconductor substrate;
• defining a capacitor region within the boundaries of the semiconductor substrate;
• forming an active circuit layer on the surface of the semiconductor substrate with a portion thereof formed in the surface of the semiconductor substrate and a portion thereof formed over the surface of the semiconductor substrate, in which is formed active circuitry and interconnects;
• forming a planarization layer of metal over the active circuit layer and electrically isolated therefrom in at least the capacitor region;
• forming a metal capacitor layer over the planarization layer within the capacitor region and having the bottom plates of a plurality of capacitors defined therein;
• forming a layer of dielectric on the bottom plates of the plurality of capacitors of a predetermined thickness;
• forming a top plate on the dielectric for each of the plurality of capacitors to define each of the plurality of capacitors, such that a portion of each of the bottom plates extends outside of the boundaries of the associated top plate;
• and
• forming a plurality of vias connected to the portion of select ones of the bottom plates and to structures beneath the planarization layer, and wherein vias are not formed within the region beneath the top plate and above the planarization layer.