Method for manufacturing non-volatile memory cells on a semiconductor substrate

A method for manufacturing non-volatile memory cells on a semiconductor substrate, comprising:

• forming active areas in said semiconductor substrate, bounded by portions of an insulating layer;
• depositing a first thin layer of tunnel oxide and a first layer of conductive material on said active areas;
• and
• defining a plurality of floating gate regions, comprising:
• forming stripes of shielding material only above pairs of alternated active areas;
• defining spacers of small width in the shelter of the side walls of the stripes thus defined;
• defining stripes of shielding material also on the active areas that lacked them;
• polishing the stripes and spacers to the same planar level;
• removing the spacers to form openings;
• and
• etching the first layer of conductive material through the openings to form a plurality of gate regions.

A semiconductor fabrication method, comprising:

• forming a plurality of first stripes from a polysilicon material over an insulated base polysilicon layer and which lie above first alternating active areas;
• forming sidewall spacers for the plurality of first stripes;
• forming a plurality of second stripes from a polysilicon material between the sidewall spacers over the insulated base polysilicon layer which lie above second alternating active areas;
• chemically mechanically polishing the first stripes, second stripes and sidewall spacers to the same planar level;
• and
• removing the sidewall spacers.

A method for semiconductor fabrication on a substrate including a plurality of active areas, comprising:

• forming a plurality of first polysilicon stripes by photolithographic techniques over an insulated base polysilicon layer and which lie above even ones of the plurality of active areas;
• and
• forming a plurality of second polysilicon stripes without the use of photolithographic techniques over the insulated base polysilicon layer and which lie above odd ones of the plurality of active areas;
• wherein the plurality of first and second polysilicon stripes have a polished upper surface at the same planar level.