Method for manufacturing non-volatile memory cells on a semiconductor substrate

A method for manufacturing non-volatile memory cells on a semiconductor substrate, comprising:

• forming active areas in said semiconductor substrate, bounded by portions of an insulating layer;
• depositing a first thin layer of tunnel oxide and a first layer of conductive material on said active areas;
• and
• defining a plurality of floating gate regions, comprising:
• defining a first floating gate from the first layer of conductive material only over pairs of alternated active areas;
• defining spacers in the shelter of the side walls of the first floating gate already defined;
• and
• completing the formation of the floating gate regions over the active areas that lacked by depositing a second layer of conductive material defining a second floating gate between the spacers.

A semiconductor fabrication method, comprising:

• forming a plurality of first polysilicon stripes to define first semiconductor gate structures over first alternating transistor active areas bounded by insulating portions;
• forming sidewall spacers for the plurality of first polysilicon stripes;
• and
• forming a plurality of second polysilicon stripes between the sidewall spacers to define second semiconductor gate structures over second alternating transistor active areas.

A semiconductor fabrication method, comprising:

• forming a plurality of first polysilicon stripes to define first semiconductor gate structures over first alternating transistor active areas;
• forming sidewall spacers for the plurality of first polysilicon stripes;
• and
• forming a plurality of second polysilicon stripes between the sidewall spacers to define second semiconductor gate structures over second alternating transistor active areas;
• wherein forming sidewall spacers comprises:
• depositing a nitride layer;
• and
• patterning the nitride layer to expose the second alternating active areas but leave the nitride layer adjacent sidewalls of the first polysilicon stripes.

A method for manufacturing non-volatile memory cells on a semiconductor substrate, comprising the steps of:

• forming active areas in said semiconductor substrate, bounded by portions of an insulating layer;
• forming a first thin layer of tunnel oxide and depositing a first layer of conductive material on said active areas;
• defining a plurality of floating gate regions, wherein the definition of the floating gate regions comprises the steps of:
• defining said first layer of conductive material in order to form a plurality of alternated stripes above pairs of active areas alternated by active areas lacking stripes;
• depositing a thin oxide layer;
• forming spacers in the shelter of the side walls of said alternated stripes, comprising the deposition of a nitride layer which is patterned together with said thin oxide layer and said tunnel oxide layer in order to expose the active areas whereon no alternated stripes are located,
• depositing a second layer of conductive material in order to fill the space between said spacers, and
• planarizing said second layer of conductive material together with said first layer of conductive material and said spacers.