Silicided buried bitline process for a non-volatile memory cell

A process of fabricating a memory cell comprising a substrate that comprises a first region and a second region with a channel therebetween, the method comprising:

• forming a gate above said channel of said substrate, wherein said gate comprises a single polysilicon layer;
• forming bitlines on both sides of said gate subsequent to said forming said gate comprising said single polysilicon layer;
• siliciding said bitlines;
• forming a charge trapping region that contains a first amount of charge;
• and
• forming a layer between said channel and said charge trapping region, wherein said layer has a thickness such that said first amount of charge is prevented from directly tunneling into said layer.