Method for implementing electro-static discharge protection in silicon-on-insulator devices

A process of forming a semiconductor structure having electrostatic discharge (ESD) protection, comprising:

• in a first doping step, doping with a first dopant a first region of a silicon layer on a silicon-on-insulator (SOI) wafer, the SOI wafer having an insulating layer at a depth below an outer surface of the silicon layer;
• forming a first gate structure and a second gate structure on the first region of the silicon layer;
• in a second doping step, doping with a second dopant a source region for the first gate structure, a drain region for the second gate structure and a shared region between the first gate structure and the second gate structure such that the second dopant does not extend through the silicon layer to the depth of the insulating layer in the shared region;
• in a third doping step, doping with a third dopant the drain region and the source region so that the third dopant extends through the silicon layer to the depth of the insulating layer.