Chip and multi-chip semiconductor device using thereof and method for manufacturing same

A chip bonding apparatus for a multi-chip semiconductor device, comprising:

• chip bonding means for stacking and bonding chips;
• and
• chip position calculating means for calculating a position of a chip to be aligned,
• wherein a chip for the multi-chip semiconductor device comprises two or more electroconductive through plugs,
• wherein one or more of said electroconductive through plugs comprise an alignment marking, and wherein when said chip is stacked by said chip bonding means, a position of the chip of said multi-chip semiconductor device is calculated by said chip position calculating means by utilizing said alignment marking.

A chip for a multi-chip semiconductor device, comprising:

• a plurality of electroconductive through plugs in one chip for the multi-chip semiconductor device,
• wherein one or more of said electroconductive through plugs comprise an alignment marking,
• wherein the chip comprises a configuration for visibly identifying said alignment marking on one of a front surface and a back surface of said chip for said multi-chip semiconductor device, and
• wherein said alignment marking comprises one of an asymmetric geometry and an asymmetric arrangement.

A chip for a multi-chip semiconductor device, comprising:

• a plurality of electroconductive through plugs in one chip for the multi-chip semiconductor device,
• wherein one or more of said electroconductive through plugs comprise an alignment marking,
• wherein the chip comprises a configuration for visibly identifying said alignment marking on one of a front surface and a back surface of said chip for said multi-chip semiconductor device, and
• wherein said electroconductive through plug for the alignment marking comprises a minimum width of a cross-section thereof of equal to or less than a minimum width of other said electroconductive through plugs.

A chip for a multi-chip semiconductor device, comprising:

• a plurality of electroconductive through plugs in one chip for the multi-chip semiconductor device,
• wherein one or more of said electroconductive through plugs comprise an alignment marking,
• wherein the chip comprises a configuration for visibly identifying said alignment marking on one of a front surface and a back surface of said chip for said multi-chip semiconductor device, and
• wherein an electric potential of at least a portion of said electroconductive through plug employed for said alignment marking is fixed.