Back end IC wiring with improved electro-migration resistance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChien-Chao Huang
Life of this patent
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Abstract
A multi-level semiconductor device wiring interconnect structure and method of forming the same to improve electrical properties and reliability of wiring interconnects including an electromigration resistance and electrical resistance, the method including forming a dielectric insulating layer over a conductive portion; forming a via opening in closed communication with the conductive portion; forming a first barrier layer to line the via opening; forming a layer of AlCu according to a sputtering process to fill the via opening to form an AlCu via including a portion overlying the first dielectric insulating layer; and, photolithographically patterning and dry etching the portion to form an AlCu interconnect line over the AlCu via.
Claims43
A method of forming a multi-level semiconductor device wiring interconnect structure according to a low temperature process comprising the steps of:
- a) forming a dielectric insulating layer over a conductive portion;
- said conductive portion comprises silicide electrical contact areas comprising a CMOS transistor portion selected from the group consisting of a gate electrode and source and drain regions;
- b) forming a via opening in closed communication with the conductive portion;
- c) forming a first barrier layer to line the via opening;
- d) then forming a layer of AlCu to fill the via opening to form an AlCu via including a portion of said AlCu layer overlying the dielectric insulating layer;
- and,
- e) forming an AlCu interconnect line from said portion of said AlCu layer over the AlCu via, wherein a second barrier layer is optionally formed on said AlCu interconnect line;
- wherein process steps c) and d) are carried out at a temperature of less than about 400 degrees Centigrade.
A method of forming a multi-level semiconductor device wiring interconnect structure according to a low temperature process to improve electrical properties including an electro-migration resistance and electrical resistance comprising the steps of:
- a) forming a dielectric insulating layer over a conductive portion;
- wherein the conductive portion comprises salicide electrical contact areas comprising a CMOS transistor portion;
- b) forming a via opening in closed communication with the conductive portion;
- c) forming a barrier layer to line the via opening;
- d) forming a layer of AlCu at a temperature less than about 400° C. to fill the via opening to form an AlCu via including a portion of said AlCu layer overlying the dielectric insulating layer;
- e) forming an AlCu interconnect line from said portion of said AlCu layer over the AlCu via;
- and,
- f) optionally forming a second barrier layer on the AlCu interconnect line.
A multi-level wiring interconnect structure for a semiconductor device comprising:
- a) a dielectric insulating layer over a conductive portion said conductive portion selected from the group consisting of tungsten, metal silicide, copper, and AlCu;
- b) an AlCu via comprising a first barrier layer formed in the dielectric insulating layer in closed communication with the conductive portion;
- c) an AlCu interconnect line disposed on and contiguous with the AlCu via;
- wherein a second barrier layer encapsulates the AlCu interconnect line on three sides.
A multi-level wiring interconnect structure for a semiconductor device comprising:
- a) a dielectric insulating layer over a conductive portion;
- wherein the conductive portion comprises salicide electrical contact areas comprising a CMOS transistor portion;
- b) an AlCu via comprising a barrier layer lining the AlCu via opening, said via opening formed in the dielectric insulating layer in closed communication with the conductive portion;
- wherein structure portions b is stacked sequentially in overlying dielectric insulating layers to comprise at least three metallization layers.
Dependencies are inferred from the claim text.