Arrangement of wiring lines including power source lines and channel wirings of a semiconductor integrated circuit having plural cells

A semiconductor integrated circuit in which a plurality of cells having respectively given functions are arranged in a first direction and a second direction, which is orthogonal to the first direction,

• wherein power source lines are arranged on peripheral portions of a cell while extending in the first direction,
• wherein the power source lines arranged on the peripheral portions of the cell are laid out at positions spaced away in the second direction from a boundary defined between cells which are arranged close to each other in the second direction,
• wherein the power source lines in the peripheral portions of the cells are formed by embedding copper films into grooves formed in an insulation film,
• wherein the power source lines are applied the same voltage, respectively, and
• wherein the power source lines of cells which are arranged close to each other include bridging portions which are bridgeable between the power source lines.

A semiconductor integrated circuit in which a plurality of cells having respectively given functions are arranged in a first direction and a second direction, which is orthogonal to the first direction,

• wherein power source lines are arranged on peripheral portions of a cell while extending in the first direction,
• wherein the power source lines arranged on the peripheral portions of the cell are laid out at positions spaced away in the second direction from a boundary defined between cells which are arranged close to each other in the second direction,
• wherein the power source lines in the peripheral portions of the cells are formed by embedding conductive films into grooves formed in an insulation film,
• wherein the power source lines are applied the same voltage, respectively,
• wherein, inwardly of peripheral portions of the cells, inter-cell lines which perform cell-to-cell connection are formed between the power source lines in the peripheral portions of the cells, and
• wherein a line width of the inter-cell lines is set larger than a line width of the power source lines.

A semiconductor integrated circuit in which a plurality of cells having respectively given functions are arranged in a first direction and a second direction, which is orthogonal to the first direction,

• wherein power source lines are arranged on peripheral portions of a cell while extending in the first direction,
• wherein the power source lines arranged on the peripheral portions of the cell are laid out at positions spaced away in the second direction from a boundary defined between cells which are arranged close to each other in the second direction,
• wherein the power source lines in the peripheral portions of the cells are formed by embedding conductive films into grooves formed in an insulation film, and
• wherein the power source lines are applied the same voltage, respectively, and
• wherein the power source lines of cells which are arranged close to each other include bridging portions which are bridgeable between the power source lines.

A semiconductor integrated circuit in which a plurality of cells having respectively given functions are arranged in a first direction and a second direction, which is orthogonal to the first direction,

• wherein power source lines are arranged on peripheral portions of a cell while extending in the first direction,
• wherein the power source lines arranged on the peripheral portions of the cell are laid out at positions spaced away in the second direction from a boundary defined between cells which are arranged close to each other in the second direction,
• wherein the power source lines in the peripheral portions of the cells are formed by embedding conductive films into grooves formed in an insulation film,
• wherein the power source lines are applied the same voltage, respectively, and
• wherein proximate power supply lines of adjacent cells are applied the same voltage, respectively.

A semiconductor integrated circuit in which a first cell and a second cell are arranged close to each other in a first direction,

• wherein the first cell includes a first line which is arranged in peripheral portions of the first cell, is extending in a second direction, orthogonal to the first direction, and is laid out at a position spaced away from a boundary defined between the first and second cells,
• wherein the second cell includes a second line which is arranged in peripheral portions of the second cell, is extending in the second direction and is laid out at position away from the boundary, and
• wherein the first and second lines are formed by embedding copper films into grooves formed in an insulation film,
• wherein the first and second lines are applied the same voltage, respectively, and
• wherein a bridging portion is arranged in the boundary to interconnect the first and second lines.

A semiconductor integrated circuit in which a first cell and a second cell are arranged close to each other in a first direction,

• wherein the first cell includes a first line which is arranged in peripheral portions of the first cell, is extending in a second direction, orthogonal to the first direction, and is laid out at a position spaced away from a boundary defined between the first and second cells,
• wherein the second cell includes a second line which is arranged in peripheral portions of the second cell, is extending in the second direction and is laid out at position away from the boundary,
• wherein the first and second lines are formed by embedding conductive films into grooves formed in an insulation film, and
• wherein a bridging portion is arranged in the boundary to interconnect the first and second lines.

A semiconductor integrated circuit comprising:

• a first cell,
• a second cell, and
• a third cell arranged close to the first and second cells in a first direction,
• wherein the first cell includes a first line which is arranged in peripheral portions of the first cell, is extending in a second direction, orthogonal to the first direction, and is laid out at a position spaced away from a first boundary defined between the first and third cells,
• wherein the second cell includes a second line which is arranged in peripheral portions of the second cell, is extending in the second direction and is laid out at a position spaced away from a second boundary defined between the second and third cells,
• wherein the third cell includes a third line which is arranged in one peripheral portion of the third cell, is extending in the second direction and is laid out at a position spaced away from the first boundary,
• wherein the third cell includes a fourth line which is arranged in another peripheral portion thereof, is extending in the second direction and is laid out at a position spaced away from the second boundary,
• wherein the absolute value of the voltage of the first and third lines applied is different from that of the second and fourth lines applied,
• wherein the first, second, third and fourth lines are formed of copper and are embedded into grooves formed in an insulation film, respectively,
• wherein the absolute value of the voltage of the first and third lines applied is the same,
• wherein the absolute value of the voltage of the second and fourth lines applied is the same,
• wherein the first, second and third cells include narrow-width lines having a line width that is narrower than the line width of the first, second, third and fourth lines, respectively,
• wherein the narrow-width lines of the first, second and third cells are arranged close to the first, second, third and fourth lines, respectively, and
• wherein each line interval between the first, second, third and fourth lines and the narrow-width lines is set to be wider than the minimum arrangement pitch of the narrow-width lines.

A semiconductor integrated circuit comprising:

• a first cell,
• a second cell, and
• a third cell arranged close to the first and second cells in a first direction,
• wherein the first cell includes a first line which is arranged in peripheral portions of the first cell, is extending in a second direction, orthogonal to the first direction, and is laid out at a position spaced away from a first boundary defined between the first and third cells,
• wherein the second cell includes a second line which is arranged in peripheral portions of the second cell, is extending in the second direction and is laid out at a position spaced away from a second boundary defined between the second and third cells,
• wherein the third cell includes a third line which is arranged in one peripheral portion of the third cell, is extending in the second direction and is laid out at a position spaced away from the first boundary,
• wherein the third cell includes a fourth line which is arranged in another peripheral portion thereof, is extending in the second direction and is laid out at a position spaced away from the second boundary,
• wherein the absolute value of the voltage of the first and third lines applied is different from that of the second and fourth lines applied, and wherein a first bridging portion is arranged in the first boundary to interconnect the first and third lines.