Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing

A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, comprising:

• fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device;
• and
• during processing steps subsequent to formation of the charge trapping dielectric charge storage layer, protecting the charge trapping dielectric flash memory cell from exposure to a level of UV radiation sufficient to deposit a non-erasable charge in the charge trapping dielectric flash memory cell,
• wherein the subsequent processing steps comprise deposition over the charge trapping dielectric flash memory cell of one or more of an interlayer dielectric layer, a cap layer and a top dielectric layer by APCVD, CVD or a spin-on method.

A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, comprising:

• fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device;
• and
• during processing steps subsequent to formation of the charge trapping dielectric charge storage layer, protecting the charge trapping dielectric flash memory cell from exposure to a level of UV radiation sufficient to deposit a non-erasable charge in the charge trapping dielectric flash memory cell, wherein the non-erasable charge is a charge which cannot be erased when a voltage sufficient to erase a bit of data written in the cell is applied to the charge trapping dielectric flash memory cell,
• wherein the processing steps subsequent to formation of the charge trapping dielectric charge storage layer comprise deposition over the charge trapping dielectric flash memory cell of one or more of an interlayer dielectric layer, a cap layer and a top dielectric layer by APCVD, CVD or a spin-on method, and at least one of the interlayer dielectric layer, cap layer or top dielectric layer comprises at least one low-K dielectric material deposited over the charge trapping dielectric flash memory cell by a non-plasma method.