US 7,118,961 B2 · Stitch and select implementation in twin MONOS array

Abstract

In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches. The stitching method can also incorporate a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase.

Claims32

Dependent claims

A stitched MONOS memory array comprising:

three resistive layers wherein said three resistive layers are vertically stacked as a bottom, middle, and top resistive layer and wherein said bottom and middle resistive layers run in parallel to each other and wherein said top resistive layer runs orthogonally to said bottom and middle resistive layers;
and
stitches periodically contacting each of said resistive layers to a respective upper conductive layer wherein said stitches comprise:
connections from said middle resistive layer to a bottom conductive layer overlying said top resistive layer;
contact/via stacks from said bottom resistive layer to a top conductive layer;
a middle conductive layer connecting cut ends of said middle resistive layer wherein said middle conductive layer overlies said bottom conductive layer and underlies said top conductive layer and wherein said middle conductive layer loops around said contact/via stacks;
and
connections from said top resistive layer to said middle conductive layer.

5 more elements

A stitched MONOS memory array comprising:

a plurality of memory cells in a MONOS memory array wherein each memory cell comprises:
a storage cell on either side of a word gate;
a diffusion junction underlying each of said storage cells wherein each of diffusions is shared with an adjacent storage cell of an adjacent memory cell;
and
a control gate overlying each of said storage cells electrically isolated from underlying said diffusion junctions wherein said control gates and said diffusions run in parallel and wherein said word gates run orthogonally to said control gates and said diffusions;
wherein word gates in said array from word lines, said control gates in said array form control gate lines, and said diffusions in said array form bit lines;
stitches periodically contacting each of said word lines, control gate lines, and bit lines by a respective upper conductive layer wherein said contacting comprises:
connections from said control gate lines to a middle conductive layer overlying said word gate lines;
contact/via stacks from said bit lines to a top conductive layer wherein said top conductive layer overlies said middle conductive layer;
a bottom conductive layer connecting cut ends of said control gate lines wherein said bottom conductive layer underlies said middle conductive layer and wherein said bottom conductive layer loops around said contact/via stacks;
and
connections from said word gate lines to said bottom conductive layer;
and
select transistors in areas of said stitching between sub-arrays of said MONOS memory cells.

11 more elements

Dependencies are inferred from the claim text.

Stitch and select implementation in twin MONOS array

Life of this patent

Stitch and select implementation in twin MONOS array

Life of this patent

Abstract

Claims32