Semiconductor wafer having different impurity concentrations in respective regions
AssigneeSamsung Electronics Co., Ltd.
InventorsYong-bae Choi, Boo-yung Huh
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Abstract
A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.
Claims17
A method of fabricating a plurality of integrated circuit semiconductor devices on a semiconductor wafer, the semiconductor wafer having a plurality of concentric regions, each concentric region having a different impurity concentration, the method comprising:
- forming a conductive layer on the semiconductor wafer;
- and
- patterning the conductive layer to form different gate patterns having different lengths in the respective concentric regions of the semiconductor wafer.
A method of fabricating a plurality of integrated circuit semiconductor devices, the method comprising:
- providing a semiconductor wafer comprising a central region, an intermediate region, and an outer region each having different respective concentrations of impurities, the central, intermediate, and outer regions being concentrically formed around a common center of the semiconductor wafer;
- forming a conductive layer on the semiconductor wafer;
- and
- patterning the conductive layer to form different gate patterns having different respective lengths in the central region, the intermediate region, and the outer region of the semiconductor wafer.
A method comprising:
- providing a semiconductor wafer having a plurality of concentrically related regions, each having a different impurity concentration;
- forming a plurality of different transistors, wherein each different transistor has a gate with a different length and is formed in one of the concentrically related regions of the semiconductor wafer.
Dependencies are inferred from the claim text.