Method and circuit of plasma damage protection
AssigneeMacronix International Co., Ltd.
InventorsMing-Hung Chou, Wen-Pin Lu
Life of this patent
Estimating the term…
Abstract
A protection circuit to discharge plasma-induced charges in a semiconductor device or integrated circuit includes a PMOS transistor and a diode. The PMOS transistor includes a substrate, a drain, a source, and a gate, the source being coupled to receive the plasma-induced charges. The diode has a positive terminal coupled to the substrate of the PMOS transistor and a negative terminal coupled the gate of the PMOS transistor.
Claims19
A protection circuit to discharge plasma-induced charges in a semiconductor device or integrated circuit, comprising:
- a PMOS transistor including a substrate, a drain, a source, and a gate, the source being coupled to receive the plasma-induced charges;
- and
- a diode having a positive terminal coupled to the substrate of the PMOS transistor and a negative terminal coupled to the gate of the PMOS transistor.
A semiconductor device or integrated circuit (IC) formed on a semiconductor substrate, comprising:
- a first part to be protected from plasma-induced charge damage;
- and
- a second part for protecting the first part from plasma-induced charge damage, including
- a PMOS transistor in an n-type well in the semiconductor substrate, including a drain, a source, and a gate, the source being coupled to receive plasma-induced charges accumulated in the first part;
- and
- a diode having a positive terminal coupled to the n-type well and a negative terminal coupled to the gate of the PMOS transistor.
A memory device, comprising:
- a memory array including a plurality of word lines;
- and
- a protection circuit for protecting the word lines from plasma-induced charge damage, including
- a PMOS transistor including a substrate, a drain, a source, and a gate, the source being coupled to receive plasma-induced charges accumulated in the word lines, and
- a diode having a positive terminal coupled to the substrate of the PMOS transistor and a negative terminal coupled to the gate of the PMOS transistor.
Dependencies are inferred from the claim text.