Dual-sided semiconductor device with a resistive element that requires little silicon surface area

A dual-sided semiconductor device formed on a wafer, the wafer having a top surface, a bottom surface, and a first dopant concentration, the device comprising:

• a doped region formed in the wafer, the doped region having a top surface, a bottom surface, and a second dopant concentration greater than the first dopant concentration;
• an upper conductive region formed in the wafer over the top surface of the doped region, the upper conductive region contacting the top surface of the wafer, a region of the wafer laterally spaced apart from the upper conductive region having the first dopant concentration;
• and
• a lower conductive region formed below the bottom surface of the doped region in the wafer, the lower conductive region having a bottom surface, a region of the wafer laterally spaced apart from the lower conductive region having the first dopant concentration, the upper conductive region, the doped region, and the lower conductive region forming a column through the wafer that electrically connects the top surface of the wafer with the bottom surface of the wafer,
• when no current flows through the column, a voltage on the top surface of the upper conductive region has a value that is substantially equal to a voltage on the bottom surface of the lower conductive region.

A dual-sided semiconductor device comprising:

• a wafer having a first surface that lies in a first plane, a second surface that lies vertically spaced apart from the first surface in a second plane, and a first dopant concentration;
• a doped region formed in the wafer, the doped region being spaced apart from the first surface of the wafer, and having a second dopant concentration greater than the first dopant concentration;
• a first conductive member having a first region and a second region, the first region contacting the doped region, the second region being vertically spaced apart from the first region and lying in the first plane, the first conductive member including a metallic material, a region of the wafer laterally spaced apart from the first conductive member having the first dopant concentration;
• and
• a second conductive member having a third region and a fourth region, the third region contacting the doped region, the fourth region being vertically spaced apart from the third region and lying in the second plane, the second conductive member including a metallic material, a region of the wafer laterally spaced apart from the second conductive member having the first dopant concentration.