US 7,115,509 B2Granted

Method for forming polysilicon local interconnects

AssigneeMicron Technology, Inc.

InventorsChun Chen, Guy Blalock, Graham Wolstenholme, Kirk Prall

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Abstract

Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

Claims14

Dependent claims

A method of fabricating a source interconnect to a memory cell, comprising:

forming a layer of dielectric material overlying a gate stack, a source region and a drain region of the memory cell;
forming a first mask layer overlying the layer of dielectric material;
patterning the first mask layer to expose a portion of the layer of dielectric material over at least the source region;
removing a portion of the exposed portion of the layer of dielectric material to form a trench shaped region and expose the source region;
removing the first mask layer;
forming a layer of polysilicon overlying the layer of dielectric material and trench shaped region to be in contact with the exposed source region;
forming a second mask layer overlying the layer of polysilicon;
patterning the second mask layer to expose a portion of the layer of polysilicon over at least the trench shaped region, wherein patterning the first and second mask layers further comprises patterning the first and second mask layers with the same pattern;
implanting ions in the exposed portion of the layer of polysilicon, thereby forming an implanted portion of the layer of polysilicon and an non-implanted portion of the layer of polysilicon;
removing the second mask layer;
and
selectively etching the layer of polysilicon to preferentially remove the non-implanted portion, thereby forming the source interconnect in the trench shaped region.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/714,752Filed 17 Nov 2003
Published: US 2005/0104114 A119 May 2005
Granted: 3 Oct 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10W 20/0698
Of conductive parts of the interconnections: local interconnections
H10B
Electronic memory devices