Sacrificial annealing layer for a semiconductor device and a method of fabrication
AssigneeIntel Corporation
InventorsMark Y. Liu, Justin K. Brask
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Abstract
Numerous embodiments of a method and apparatus for a sacrificial annealing layer are disclosed. In one embodiment, a method of forming a sacrificial annealing layer for a semiconductor device comprises forming one or more sacrificial layers on at least a portion of the top surface of a semiconductor device, annealing at least a portion of the device, and removing a substantial portion of the one or more sacrificial layers, where the removing results in no substantial physical alterations to the device.
Claims27
A method of forming a semiconductor device, comprising:
- forming a sacrificial layer on at least a portion of a top surface of an interlayer dielectric of the semiconductor device to a thickness sufficient to prevent the interlayer dielectric from changing phases during a laser annealing process, wherein the sacrificial layer comprises a phosphorous doped polysilicon layer;
- annealing at least a portion of the semiconductor device;
- activating a dopant implanted in the semiconductor device;
- and
- removing a substantial portion of the sacrificial layer, wherein the removing results in no substantial physical alterations to the semiconductor device.
A method of annealing a silicon wafer, comprising:
- at least partially forming a transistor on a silicon wafer;
- forming a sacrificial layer on at least a portion of an interlayer dielectric of the silicon wafer to a thickness sufficient to prevent the interlayer dielectric from changing phases during a laser annealing process, wherein at least a portion of the sacrificial layer is comprised of phosphorous doped polysilicon;
- annealing at least a portion of the silicon wafer;
- activating a dopant implanted in the silicon wafer;
- and
- removing a substantial portion of the sacrificial layer
- wherein the removing results in no substantial physical alterations to the transistor.
A method comprising:
- forming a sacrificial layer on at least a portion of a top surface of an interlayer dielectric of a transistor to a thickness sufficient to prevent the interlayer dielectric from changing phases during a laser annealing process, wherein the sacrificial layer comprises a phosphorous doped polysilicon layer;
- laser annealing at least a portion of the transistor;
- absorbing, by the sacrificial layer, heat generated during the laser annealing;
- activating a dopant implanted in a source region and a drain region of the transistor;
- and
- removing a substantial portion of the sacrificial layer, wherein the laser annealing and removing do not substantially physically alter the transistor.
Dependencies are inferred from the claim text.