Standard cell back bias architecture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing-Hao Shaw, Chih Hung Wu, Charlie Chueh
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Abstract
An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.
Claims16
An apparatus, comprising:
- a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein the first and second doped wells have opposite dopant types, and wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential;
- and
- a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potentials, wherein the first tap cell doped region has the same dopant type as the first doped well but a higher dopant concentration relative to the first doped well, and wherein the second tap cell doped region has the same dopant type as the second doped well but a higher dopant concentration relative to the second doped well.
An apparatus, comprising:
- an N well located in a substrate;
- a P well located in the substrate proximate the N well;
- a tap cell including an N+ doped region in the N well and a P+ doped region in the P well;
- a plurality of CMOS device cells each including a plurality of CMOS transistor devices each having source/drain regions in a corresponding one of the N well and the P well;
- power supply and ground interconnects configured to connect the source/drain regions of ones of the plurality of CMOS transistor devices at least indirectly to a corresponding one of a power supply and ground to bias the connected source/drain regions with a corresponding one of a power supply potential and a ground potential;
- and
- a first back-bias interconnect and a second back-bias interconnect configured to connect the N well and the P well, respectively, at least indirectly to first and second back-bias sources to bias the N well and the P well with a first and second back-bias potential, respectively, that are each a different potential relative to the power supply and ground potential.
Dependencies are inferred from the claim text.