Programmable logic devices providing reduced power consumption

A logic circuit, comprising:

• a first input node operable to receive a first stream of data values;
• a second input node operable to receive a second stream of data values;
• and
• a programmable logic circuit coupled to the first and second input nodes and operable in a dual-edge-triggered mode to store a first data value on the first input node in response to an edge of a clock signal and to store a second data value on the first input node in response to an opposite edge of the clock signal, the stored first and second data values being sequentially provided on a first output, and the logic circuit operable in a single-edge-triggered mode to store the first data value on the first input node in response to the edge of the clock signal and to provide the stored value on the first output and operable to store the second data value on the second input node in response to the edge of the clock signal and to provide the stored value on a second output.

A configurable logic circuit, comprising:

• a first input node operable to receive a first stream of data values;
• a second input node operable to receive a second stream of data values;
• a first output node;
• a second output node;
• a clock node operable to receive a clock signal having first-type and second-type edges;
• and
• a flip-flop circuit coupled to the input nodes, output nodes, and clock node and, in a dual-edge-triggered mode, operable to,
• latch a first data value on the first input node and provide the latched first data value on the first output node in response to a first-type edge of the clock signal, and
• latch a second data value on the first input node and provide the latched second data value on the first output node in response to a second-type edge of the clock signal
• and, in a single-edge-triggered mode, operable to
• latch a first data value on the first input node and provide the latched value on the first output node responsive to the first-type edge of the clock signal, and
• latch a second data value on the second input node and provide the latched value on the second output node responsive to the first-type edge of the clock signal.

A logic circuit, comprising:

• first and second circuit input nodes;
• first and second circuit output nodes;
• a first flip-flop having an input node coupled to the first circuit input node, a clock node, and an output node;
• a second flip-flop having an input node, a clock node, and an output node coupled to the second circuit output node;
• a first multiplexor operable to couple the clock node of the second flip-flop to a clock signal in a first operational mode and to an inverted clock signal in a second operational mode;
• a second multiplexor operable to couple the input node of the second flip-flop to the first circuit input node in a second operational mode and to the second circuit input node in the first operational mode;
• and
• a third multiplexor operable to couple the output node of the first flip-flop to the first circuit output node in the first operational mode and to alternately couple the output nodes of the first and second flip-flops to the first circuit output node in the second operational mode.

A programmable logic block, comprising:

• a logic circuit, comprising,
• a first input node operable to receive a first stream of data values;
• a second input node operable to receive a second stream of data values;
• and
• a programmable logic circuit coupled to the first and second input nodes and operable in a dual-edge-triggered mode to store a first data value on the first input node in response to an edge of a clock signal and to store a second data value on the first input node in response to an opposite edge of the clock signal, the stored first and second data values being sequentially provided on a first output, and the logic circuit operable in a single-edge-triggered mode to store the first data value on the first input node in response to the edge of the clock signal and to provide the stored value on the first output and operable to store the second data value on the second input node in response to the edge of the clock signal and to provide the stored value on a second output.

An integrated circuit, comprising:

• a programmable logic block, comprising,
• a logic circuit, comprising:
• a first input node operable to receive a first stream of data values;
• a second input node operable to receive a second stream of data values;
• and
• a programmable logic circuit coupled to the first and second input nodes and operable in a dual-edge-triggered mode to store a first data value on the first input node in response to an edge of a clock signal and to store a second data value on the first input node in response to an opposite edge of the clock signal, the stored first and second data values being sequentially provided on a first output, and the logic circuit operable in a single-edge-triggered mode to store the first data value on the first input node in response to the edge of the clock signal and to provide the stored value on the first output and operable to store the second data value on the second input node in response to the edge of the clock signal and to provide the stored value on a second output.

An electronic system, comprising:

• an integrated circuit, comprising,
• a programmable logic block, comprising,
• a logic circuit, comprising,
• a first input node operable to receive a first stream of data values;
• a second input node operable to receive a second stream of data values;
• and
• a programmable logic circuit coupled to the first and second input nodes and operable in a dual-edge-triggered mode to store a first data value on the first input node in response to an edge of a clock signal and to store a second data value on the first input node in response to an opposite edge of the clock signal, the stored first and second data values being sequentially provided on a first output, and the logic circuit operable in a single-edge-triggered mode to store the first data value on the first input node in response to the edge of the clock signal and to provide the stored value on the first output and operable to store the second data value on the second input node in response to the edge of the clock signal and to provide the stored value on a second output.

A method, comprising:

• during a first operational mode, storing a first data value from a first input signal in response to a first clock edge having a first polarity;
• and
• during the first operational mode, storing a second data value from the first input signal in response to a second clock edge having a second polarity that is opposite to the first polarity;
• during a second operational mode, storing a first data value from a first input signal in response to the first clock edge having a first polarity;
• and
• during the second operational mode, storing a second data value from a second input signal in response to the first clock edge having the first polarity.