Apparatus and method for split transistor memory having improved endurance

A semiconductor memory device, comprising:

• an array having memory cells for storing a desired logic state, each cell further comprising first and second adjacent field effect transistors (FETs) having respective source/drain regions and a common floating gate structure that is spaced apart from the source/drain regions of the first FET by a first distance, and spaced apart from the source/drain regions of the second FET by a second distance, wherein the first distance is less than the second distance;
• wherein each of the respective source/drain regions further comprise a first source/drain region and a spaced apart second drain region configured in a columnar structure extending upwardly from an underlying substrate, and further wherein a separation layer is interposed between the first source/drain region and the second drain region;
• and
• wherein the first source/drain region and the second drain region are comprised of a semiconductor material having an N+ conductivity, and further wherein the separation layer is comprised of a semiconductor material having a P− conductivity.

A method of forming a memory device having a plurality of interconnected memory cells, each cell comprising:

• positioning a first columnar structure on a substrate having at least two source/drain regions formed in it;
• positioning a second columnar structure on the substrate having at least two source/drain regions formed in it, wherein the second columnar structure is spaced apart from the first columnar structure;
• forming a gate structure between the first structure and the second structure;
• and
• interposing a floating gate structure between the first structure and the gate structure and between the second structure and the gate structure, the floating gate structure being positioned closer to selected one of the first structure and the second structure.

A method of forming a memory device having a plurality of interconnected memory cells, each cell comprising:

• positioning a first columnar structure on a substrate;
• positioning a second columnar structure on the substrate that is spaced apart from the first columnar structure;
• forming a gate structure between the first structure and the second structure;
• and
• interposing a floating gate structure between the first structure and the gate structure and between the second structure and the gate structure, the floating gate structure being positioned closer to selected one of the first structure and the second structure;
• wherein positioning a first and second columnar structures on the substrate further comprises positioning the first and second columnar structures on a silicon substrate that is doped to have a first conductivity.

A method of forming a memory device having a plurality of interconnected memory cells, each cell comprising:

• positioning a first columnar structure and a second columnar structure on the substrate that is spaced apart from the first columnar structure, wherein positioning a first and second columnar structures on the substrate further comprises,
• forming a first source/drain region having a first conductivity on the substrate,
• forming a second source/drain region proximate to the first source/drain region, the second source/drain region having the first conductivity, and
• interposing a separation layer between the first source/drain region and the second source/drain region;
• forming a gate structure between the first structure and the second structure;
• and
• interposing a floating gate structure between the first structure and the gate structure and between the second structure and the gate structure, the floating gate structure being positioned closer to selected one of the first structure and the second structure;
• wherein forming a second source/drain region proximate to the first source/drain region comprises forming a source/drain region having an N+ conductivity above the first source/drain region.