Dual damascene method for ultra low K dielectrics

A method for forming a copper filled dual damascene formed in a low-K dielectric insulating layer to prevent damage during an ashing process comprising the steps of:

• providing a semiconductor process wafer comprising a via opening extending though a thickness portion of at least one dielectric insulating layer;
• depositing a first dielectric layer stack comprising at least one dielectric layer according to a first CVD process over the via opening to close off and selectively seal an upper portion of the via opening;
• depositing a second dielectric layer stack according to a second CVD process comprising at least one dielectric layer to form a hardmask over and contacting the first dielectric layer stack;
• the first CVD process comprises at least one of a lower deposition temperature and a higher pressure compared to the second CVD process to produce a lower etching resistance in a reactive ion etching process,
• photolithographically patterning an overlying photoresist layer and reactive ion etching through a thickness of the hardmask and the first dielectric layer stack to form a trench opening etching pattern overlying and encompassing the via opening while leaving the via opening sealed;
• carrying out a plasma ashing process to remove the photoresist layer without exposing an interior portion of the via opening;
• and,
• etching according to a second reactive ion etching process through a thickness portion of the at least one dielectric insulating layer to form a dual damascene opening.