Gate electrode for FinFET device
AssigneesInfineon Technologies AG, Texas Instruments Incorporated
InventorsNirmal Chaudhary, Thomas Schulz, Weize Xiong, Craig Huffman
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AssigneesInfineon Technologies AG, Texas Instruments Incorporated
InventorsNirmal Chaudhary, Thomas Schulz, Weize Xiong, Craig Huffman
Estimating the term…
In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having a more uniform thickness may be formed over the conductive layer. Because the masking layer has a more uniform thickness, the masking layer may easily be patterned without causing damage to the underlying materials. These techniques may be used to fabricate, among other things, a FinFET without parasitic spacers formed around the fins and the source/drain regions.
A method of forming a FinFET, the method comprising:
A method of forming a FinFET, the method comprising:
A method of forming a FinFET, the method comprising:
A transistor formed on a substrate, the transistor comprising:
A transistor formed on a substrate, the transistor comprising:
Dependencies are inferred from the claim text.