US 7,080,344 B2 · Coding of FPGA and standard cell logic in a tiling structure

Abstract

A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect's type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

Claims20

Dependent claims

A method for creating a logic design using a register transfer language, said method comprising:

upon a declaration of a signal interconnect, defining a language extension of a register transfer language for the signal interconnect based on a signal interconnect type;
storing different signal interconnect types in a same design file;
and creating a logic design by partitioning between different types of cells in the logic design, wherein the different types of cells are based on the different signal interconnect types as described byte language extensions.

Dependencies are inferred from the claim text.

Coding of FPGA and standard cell logic in a tiling structure

Life of this patent

Coding of FPGA and standard cell logic in a tiling structure

Life of this patent

Abstract

Claims20